In general, a layer 2 switch device uses one of two switch architectures: one is a distributed switch architecture in which switching devices are mounted on multiple line cards with a frame switch function distributed on the line cards, and the other is a centralized switch architecture in which one centralized switch card and multiple line cards are used with one switching device provided on the switch card to switch frames from multiple connected line cards in a centralized manner.
The switching device described above includes a search table composed of entries each composed of an address and a port number. In many cases, this search table is managed independently by each switching device.
A link aggregation (hereinafter called LAG) function is a function that aggregates multiple links into one, and a switching device having this LAG function has a table that manages the LAG configuration (hereinafter called a LAG management table). The LAG management table is a table that manages a relation between LAG groups and ports belonging to the LAG groups. As with the search table described above, this LAG management table is included in each switching device in most cases and is managed independently by each switching device.
When the centralized switch architecture is used, the LAG management table is included in the centralized switch card, to which multiple line cards are connected, for integrated management. In this case, a link aggregation extending across two or more line cards can be configured for connection to an external communication device by centralizing the statuses of the ports of the line cards configuring the LAG in the centralized switch card and by managing the statuses of the ports with the use of one LAG management table provided in the centralized switch.
The following describes the above-described operation for a switch device using conventional distributed switch architecture, with reference to FIG. 4 and FIG. 5. Referring to FIG. 4, it is assumed that, when a port 1212 is normal, the port 1212 is selected as the output port of a frame to be sent to a host 4 according to the LAG distribution algorithm.
At this time, if the port 1212 fails as shown in FIG. 4, a LAG management table 623 on a line card 62 is updated from the table at the top (normal time) of FIG. 5 to the table at the bottom (failure time). As a result, a port 1221 is selected as the output port, and a frame is transferred to a line card 63.
However, because a LAG management table 633 on the line card 63, which has a port constituting the same LAG, does not have means for knowing that the port 1212 of the line card 62 has failed, the table is not updated so that the two tables become inconsistent. On the line card 63, because an output port is selected according to the same distribution algorithm as that of the line card 62 based on the LAG management table 633 which is not updated, the failing port 1212 is determined as the output port. This creates a problem in that a frame cannot be sent to a communication device 2.
One of the means for making the status of the LAG management table consistent among multiple line cards is that information (LAG management information) on a status change in the LAG management table (a port entry is disabled when a port belonging to a LAG fails; a port entry is enabled when the port belonging to a LAG recovers) is notified to, or confirmed by, the CPU (Central Processing Unit) 61 to reflect a change in the content of the LAG management table on one line card onto the LAG management table on the other line card.
A LAG is described in the following patent documents.
[Patent Document 1] Japanese Patent Kokai Publication No. JP-P2006-295934A
[Patent Document 2] Japanese Patent Kokai Publication No. JP-P2006-295935A
The following analysis is given by the present invention. The disclosures of the above-mentioned Patent Documents 1-2 are herein incorporated by reference thereto, and regarded as part of the disclosure of the present invention.
When a port constituting a LAG fails in the distributed switch architecture in which there is no centralized switch card as described above, the LAG management tables on all line cards must be updated to make them consistent, to distribute frames only to a normal port.
However, in the distributed switch architecture described above in which the LAG management table on each line card is managed independently, there is no means for notifying the failure status to the line card other than the line card to which the failing port belongs. For this reason, the LAG table cannot be updated and, as a result, an inconsistency exits between the LAG table on the line card to which the failing port belongs and the LAG management table on the other line card. In this case, when the failing port is selected as the output port on a line card other than the line card to which the failing port belongs, frames sometimes cannot be sent. This means that a LAG extending across line cards cannot be built.
The above-described means for making the LAG management table status consistent using the CPU 61 involves software processing by the CPU 61. This software processing has a processing performance problem because it takes time to detect a change in the port status and there is a delay in reflecting a change in the LAG management tables 623 and 633. Another problem is that a failure of the CPU 61, if generated, results in the failure of the management of the LAG management tables 623 and 633.